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AN1017/1098 1/38 application note using the st7 universal serial bus microcontroller by microcontroller division applications 1 introduction 1.1 what is usb figure 1. a usb topology example the universal serial bus is an industry standard that brings plug-and-play technology to the pc peripherals. the key features are: n ease of use: peripherals will be detected and configured automatically when physically attached, hot plugging allows adding and removing devices without powering down or rebooting, using a single connector for all devices. n built in power distribution for low power devices. n port expansion: enables up to 127 different pc peripherals to be plugged to a pc. monitor kbd pc mouse printer hub hub host/hub phone speakers 1
2/38 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 what is usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 device enumeration and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 usb reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1.1 dma buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1.2 ctr interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 receive and transmit procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.1 receive procedure on endpoint 0 . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.2 transmit procedure on endpoint 0 and endpoint 1 . . . . . . . 10 3.3 data transfer with endpoint 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.1 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.2 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.3 status stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 data transfer with endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.1 interrupt transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 suspend/resume operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.1 entering suspend state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.2 exiting suspend state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 remote wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 program flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 program architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 usb initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 usb polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 usb interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1
3/38 using the st7 universal serial bus microcontroller 5.5 transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5.1 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.5.2 data stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6 status stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6.1 status in stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6.2 status out stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.7 usb reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.8 start of frame event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
using the st7 universal serial bus microcontroller 4/38 1.2 scope the st7 usb interface is a universal serial bus peripheral that provides a means of con- necting a pc peripheral serving as a function to a pc host. it supports low speed data trans- fers. objectives: this application note describes an example firmware for interaction with the usb interface hardware and support interactions between a usb device and a host system. the usb function firmware is divided into three layers as shown in figure 2. usb function layer : this firmware layer implements the functionality provided by the device. usb logical device layer: this firmware layer implements all standard usb requests and low speed data transfers. usb bus interface layer: this firmware layer is the interface between the usb logical device layer and the usb interface hardware. the usb logical device is discussed in detailed in this application note. figure 2. usb software model the following chapters provide flowcharts and description of the firmware routines needed to support the usb device operations: ? device enumeration and configuration ? data transfers ? power management function usb logical device usb bus interface usb device client sw usb system sw usb bus interface usb host physical (wire) communications flow logical (sw) communications flow capability provides common device abstraction physical interface, signaling usb cable
5/38 using the st7 universal serial bus microcontroller 2 device enumeration and configuration when a usb device is attached, the host issues a reset signal. when the reset signal is re- leased, the device enters the unenumerated state. 2.1 usb reset the usb reset is independent from the chip reset. a usb reset signal resets the usb inter- face peripheral but not the st7 core and other peripherals. when a usb reset signal is detected on the bus, the reset bit in the istr register is set and an usb interrupt is generated. all the usb interface registers are reset. 2.2 enumeration the host performs a bus enumeration to identify the attached device and to assign a unique address to it. the device responds to the requests sent by the host during the enumeration process on its default pipe (endpoint 0). enumeration steps: 1. get device descriptor. the host send a get device descriptor request. the device replies with its device descriptor to report its attributes (device class, maximum packet size for endpoint zero). 2. set address a usb device uses the default address after reset until the host assigns a unique address using the set address request. the firmware writes the device address assigned by the host in the daddr register. note: the firmware must write the device address only after completion of the set address operation because the status stage that concludes the control transfer still uses the default ad- dress. 3. get configuration the host sends a get configuration. the device replies with its configuration descriptor, inter- face descriptor and endpoint descriptor. the configuration descriptor describes the number of interfaces provided by the configuration, the power source (bus or self powered) and the max- imum power consumption of the usb device from the bus. the interface descriptor describes the number of endpoints used by this interface. the endpoint descriptor describes the transfer type supported and the bandwidth requirements. others class-specific descriptors may be returned by the device depending on the function implemented.
using the st7 universal serial bus microcontroller 6/38 4. set configuration the host assigns a configuration value to the device based on the configuration information. the device is then in configured state and can draw the amount of power described in the con- figuration descriptor. the device is now configured and ready to be used.
7/38 using the st7 universal serial bus microcontroller 3 data transfer 3.1 overview the st7 usb interface can receive data on endpoint 0,1,2 and send data through endpoint 0,1,2 (endpoint 2 may not be available on all st7 microcontrollers). the transfer types sup- ported by the st7 are: 1. control transfer with endpoint 0 (setup, out and in tokens) 2. interrupt transaction with endpoint 1 (in token) note: transmission and reception on endpoints 1 and 2 may be supported, depending on the microcontroller type and the conditional compilation options chosen (see condcomp.h file). 3.1.1 dma buffers the received and sent data are stored in ram buffers assigned to the dma of the usb inter- face. dma buffers are a contiguous ram area. the firmware must write the starting address of the dma memory area in the dmar register and in the da7 and da6 bits of the idr register. the six least significant bits of the idr register are managed by hardware. for detailed information on the mapping, see usb interface chapter of the st7 data sheet. 3.1.2 ctr interrupt when a correct transfer operation has been performed, a ctr interrupt (see ctr bit in the istr register) is generated. the following events generate a ctr interrupt: 1. ack handshake returned by the host after a data has been sent in response to an in token 2. valid setup or out token received followed by a data packet and ack handshake re- turned to the host by hardware figure 3 describes the interaction between the received token packet and the hardware reg- ister of the st7 usb interface. the token packet contains: 1. pid field specifying either in, out or setup token 2. addr and endp fields identifying the endpoint that will receive the data packet following the token packet.
using the st7 universal serial bus microcontroller 8/38 figure 3. token packet reception the firmware must determine the data transfer direction and the endpoint number which has sent or received data by reading the idr and pidr registers. the following table shows the data transfer direction corresponding to the each pid. pid name data transfer direction setup, out from host to device in from device to host pid addr endp crc5 write into must match with endpoint reception register token packet tp3 tp2 - - - - - - ctrl dtog rx stat [1] stat [0] ena[3] ena[2] ena[1] ena[0] - add6 add5 add4 add3 add2 add1 add0 7 daddr register idr register must match with
9/38 using the st7 universal serial bus microcontroller 3.2 receive and transmit procedures 3.2.1 receive procedure on endpoint 0 endpoint 0 receive data operation is explained in the figure 4. figure 4. reception procedure when the device receives a setup or an out pid, if the device address and the endpoint number contained in the setup or out packet match with the address written in daddr register and one of the two endpoint numbers, the following operations are performed: 1. if the stat_tx bits of the endpoint addressed are set to stall, a stall handshake is re- turned by hardware to the host. 2. if the stat_tx bits of the endpoint addressed are set to nak, a nak handshake is re- turned by hardware to the host. 3. if the stat_tx bits of the endpoint addressed are set to valid, a dma request on that endpoint is performed. data are transferred in the dma buffer. if the crc is correct, an ack handshake is returned by hardware to the host, dtog_rx bit is toggled and the hardware disables the endpoint by setting the stat_rx bits to 10 (nak). the ctr bit in istr register is set, causing an interrupt if enabled. firmware writes valid in stat_rx bits of ep0rb register to enable reception valid setup/out token received hardware replies ack and generates a ctr interrupt ctr interrupt firmware reads: 1. ep1 and ep0 bits of idr register to determine which endpoint has generated the interrrupt 2. tp3 and tp2 bits of pidr register to determine the token type received firmware clears ctr bit of istr register iret firmware performs data processing
using the st7 universal serial bus microcontroller 10/38 the following table summarizes the behavior of the usb interface when a setup/out token is received by endpoint 0. 3.2.2 transmit procedure on endpoint 0 and endpoint 1 the transmit operation is explained in the figure 5. figure 5. transmission procedure when the device receives an in pid, if the device address and the endpoint number contained in the in packet match with the address written in daddr register and one of the two endpoint numbers, the following operations are performed: 1. if the stat_tx bits of the endpoint addressed are set to stall, a stall handshake is re- turned by hardware to the host. stat_rx1 stat_rx0 action performed by hardware when setup/out token received 0 0 no action. usb interface ignores the received token 0 1 stall handshake returned 1 0 nak handshake returned 11 1. data received 2. stat_rx0 reset 3. ack handshake returned firmware writes: 1. data in the dma endpoint transmit buffer 2. number of bytes to transmit in the tbcn bits of epnra register 3. valid in stat_tx bits of epnra register to enable transmission valid in token received hardware returns a data packet ack received: ctr interrupt firmware reads: 1. ep1 and ep0 bits of idr register to determine which endpoint has generated the interrrupt 2. tp3 and tp2 bits of pidr register to determine the token type received firmware clears ctr bit of istr register iret
11/38 using the st7 universal serial bus microcontroller 2. if the stat_tx bits of the endpoint addressed are set to nak, a nak handshake is re- turned by hardware to the host. 3. if the stat_tx bits of the endpoint addressed are set to valid, a dma request on that endpoint is performed. a data0 or data1 data packet is sent according to the dtog_tx bit in epnra register. after the last byte in the dma buffer is sent, the crc is sent by hardware. upon receipt of ack handshake from the host, dtog_tx bit is toggled and the hardware dis- ables the endpoint by setting the stat_tx bits to 10 (nak). the ctr bit in istr register is set, causing an interrupt if enabled. the following table summarizes the behavior of the usb interface when a in token is received by endpoint 0. 3.3 data transfer with endpoint 0 endpoint 0 supports control transfers. there are two types of control transfers: 1. control transfer with data phase 2. no-data control transfer. as a consequence, a control transfer may have three transaction stages: 1. setup stage 2. data stage (not for no-data control transfer) 3. status stage the figure 6 shows an example of control transfer with one data in stage (only 8 data bytes are exchanged). stat_tx1 stat_tx0 action performed by hardware when in token received 0 0 no action. usb interface ignores the received token 0 1 stall handshake returned 1 0 nak handshake returned 11 1. data sent 2. stat_tx0 reset
using the st7 universal serial bus microcontroller 12/38 figure 6. control transfer 3.3.1 setup stage the host sends a setup token followed by a data field of 8 bytes. endpoint 0 must always be able to accept a setup token. to support this requirement, the status bits stat_rx0 and stat_rx1 of the ep0rb register must be re-write to valid after every data reception on endpoint 0. the hardware interface acks the valid setup token and generates a correct transfer (ctr) usb interrupt. in the figure 7 endpoint number is 0 and the pid type is setup. packet # sync setup addr endp crc5 setup token 231 00000001 0xb4 0x00 0x0 0x08 packet # sync data0 data crc16 setup data token 232 00000001 0xc3 80 06 00 01 00 00 40 00 0x8829 packet # sync ack ack handshake from st7 233 00000001 0x48 packet # sync in addr endp crc5 in token of data in stage 234 00000001 0x96 0x00 0x0 0x08 packet # sync data1 data crc16 data returned by st7 235 __000001 0xd2 12 01 00 01 00 00 00 08 packet # sync ack ack handshake from host 236 00000001 0x48 packet # sync out addr endp crc5 out token of status out stage 237 00000001 0x87 0x00 0x0 0x08 packet # sync data1 data crc16 zero length data packet sent by host 238 00000001 0xd2 0x0000 packet # sync ack ack handshake from st7 239 00000001 0x48 s e t u p d a t a s t a t u s
13/38 using the st7 universal serial bus microcontroller figure 7. control transfer (setup stage) the firmware must decode the 8 bytes received in the data packet following the setup token. the following table describes the 8 bytes of a setup data packet. parsing these bytes, the firmware determines: 1. if there is a data phase looking at the wlength value 0 = no-data control transfer 2. the direction of the following data phase (if present) looking at bit 7 of the bmrequesttype: 0 = host to device (out data stage) 1 = device to host (in data stage) if no data stage follows the setup stage, the firmware gets ready to perform the status stage. offset field size description 0 bmrequesttype 1 used by firmware to determine the data xfer direction, the type of the request (standard, class, vendor) and the recipient of the request (device, interface, endpoint). 1 brequest 1 request code. 2 wvalue 2 varies according to the request. 4 windex 2 varies according to the request. 6 wlength 2 if = 0, no-data control transfer. used by firmware to know how many bytes have to be sent or received by the device. into tp2-3 bits of pidr must match with daddr, otherwise no answer send to host must match with e0a[3:0] bits of ep0ra, otherwise no answer sent to host checked, if not correct: error interrupt dtog_rx set to 0 by hw data transferred into dma buffers checked, if not correct: error interrupt setup packet data packet ack pid addr endp crc5 data0 pid data crc16
using the st7 universal serial bus microcontroller 14/38 3.3.2 data stage the data stage can be either from the host to the device or from the device to the host. it con- sists of one or more in or out transactions. the amount of data to be sent during the data stage and its direction are specified during the setup stage. if, for instance, the amount of data to be transferred is 18 bytes, the data stage will have two data transfer of 8 bytes (maximum data payload) and a data transfer of 2 bytes. 3.3.3 status stage the status stage of a control transfer is the last operation in the sequence. it can be detected by the device when there is a change in direction of data flow from the previous stage. the status stage reports to the host the outcome of previous setup and data stages of the transfer. the status stage can use either in or out tokens. for a control read (using in token during data stage), the host send an out token followed by a zero length data packet and waits for the ack handshake from the device. for a control write (using out token during data stage), the host send a in token, the device returns a zero length data packet and the host returns an ack handshake. 3.4 data transfer with endpoint 1 endpoint 1 supports interrupt transaction. 3.4.1 interrupt transaction when the function has some data to return to the host through the interrupt pipe, it must write this data in the dma buffer and enable endpoint 1 in transmission by setting the ep1ra to valid. the host polls endpoint 1 with a polling interval given in the endpoint descriptor by sending an in token. the hardware interface replies with stall, nak or data .
15/38 using the st7 universal serial bus microcontroller 4 power management the st7 supports the following usb power management features: ? suspend/resume ? remote wake-up 4.1 suspend/resume operations 4.1.1 entering suspend state when no activity is seen on the bus for more than 3 ms, the st7 enters suspend state. this functionality is implemented through the usb susp interrupt. when this interrupt occurs the corresponding bmusbintflag bit is set and the firmware must then set the susp bit in ctrl register to enter suspend state. the firmware main loop checks if the susp bit is set to halt the microcontroller in order to meet the power requirement of the usb specification. the whole application must not draw more than 500 a from the usb bus in suspend state (only in bus powered applications).
using the st7 universal serial bus microcontroller 16/38 figure 8. entering suspend mode program main loop susp interrupt routine iret susp interrupt set susp bit in the ctrl register susp bit in the ctrl re g ister set halt n y vr02127a clear susp bit of the istr register
17/38 using the st7 universal serial bus microcontroller 4.1.2 exiting suspend state the microcontroller exits halt mode when one of the three following events occur. 1. resume signal on the usb bus. the microcontroller exits halt mode and jumps to the usb end suspend interrupt routine. 2. usb reset on the usb bus. the microcontroller exits halt mode and jumps to the usb reset interrupt routine. 3. an external interrupt event is generated through an i/o port pin by the application. then the microcontroller exits from halt mode and jumps to the corresponding interrupt routine. 4.2 remote wake-up when the st7 is in suspend state and an enabled external interrupt occurs, it can initiate a resume signaling to wake up the system. the function restarts the cpu clocks and executes the external interrupt routine. within this external interrupt routine, the firmware clears the susp bit in the ctrl register and sets the resume bit in the ctlr register to force the resume signal on the usb bus. the firmware must keep the resume bit set for at least 20 ms.
using the st7 universal serial bus microcontroller 18/38 figure 9. remote wake-up program external interrupt routine suspend state clear susp bit in the ctrl register set resume bit in the ctrl register wait for at least 20 ms clear resume bit in the ctrl register awake state external interrupt iret vr02127b
19/38 using the st7 universal serial bus microcontroller 5 program flow this chapter provides flowcharts of a low speed usb interface basic driver. these flowcharts describe the operations that the firmware must do to support data transfers used by standard usb requests. 5.1 program architecture the usb events are managed by interrupt. a single interrupt vector is used for the usb inter- rupt sources. the firmware must determine the interrupt origin by reading the istr register, set a bit in a software register and clear the interrupt flag. the usb polling routine reads the software register to determine the usb interrupt source and jump to the corresponding interrupt routine.
using the st7 universal serial bus microcontroller 20/38 figure 10. usb program architecture before entering the main loop, the firmware must initialize the usb interface hardware. usb interrupt routine usb routines data in stage transfert setup main loop u sb polling: checks if a software interrupt flag is set and jum ps to the corresponding routine firm ware finds out the origin of the usb interrupt firm ware sets the software flag corresponding to the usb interrupt source firm ware clears the interrupt flag in theistr register iret usb interrupt vr02127c
21/38 using the st7 universal serial bus microcontroller 5.2 usb initialization this routine initializes the hardware and resets the software registers to enable the usb inter- face. the initialization steps are: 1. set the starting address of the endpoint dma buffers 2. enable endpoint 0 in reception 3. write interrupt mask register 4. power on the internal 3.3v regulator to supply the external pull-up resistor used for detec- tion by a hub. 5. enable interrupts 5.3 usb polling this routine is in the main loop and checks if a bit in the software interrupt register is set and jumps to the corresponding interrupt routine. the following figure describes the interaction be- tween the usb polling routine in the main loop and the other usb routines.
using the st7 universal serial bus microcontroller 22/38 figure 11. program flow overview main loop u sb initialization u sb polling transfert usb reset sof event setup stage data o ut stage status in stage data in stage status out stage out token sof interrupt occurred setup token reset interrupt occurred in token out token ctr interrupt occurred in token vr02127d
23/38 using the st7 universal serial bus microcontroller 5.4 usb interrupt the usb interrupt routine copies the istr register masked by the imr register value to a soft- ware register and clears the bit of the istr register corresponding to the pending interrupt. the usb polling routine in the main loop checks if an interrupt software flag is set to execute the corresponding interrupt routine.
using the st7 universal serial bus microcontroller 24/38 figure 12. usb interrupt routine start w rite bm usbintflag with the value of the istr register m asked with the im r register bmusbintflag sof bit set clear so f bit of the istr register y n bmusbintflag reset bit set clear reset bit of the istr register y n bmusbintflag esusp bit set clear esusp bit of the istr register y n bmusbintflag io vr bit set clear io vr bit of the istr register y n bmusbintflag err bit set clear err bit of the istr register y n bmusbintflag ctr bit set read pid name (pidr register) and endpoint number (idr register) y n clear ctr bit of the istr register bmusbintflag d o v r bit set y iret clear dovr bit of the istr register vr02127e
25/38 using the st7 universal serial bus microcontroller 5.5 transfer this routine is called by usb polling when the ctr (correct transfer) bit in the istr register has been set. it determines which type of token has been received and by which endpoint number (zero or one) and jumps to the routine corresponding to the current usb event: setup stage, data in stage, data out stage, status in stage, status out stage on endpoint 0. figure 13. transfer routine start clear ctr bit of bmusbintflag endpoint number = 0 pid = setup endpoint number = 1 setup stage a b pid = in pid = out error pid = in data sent through pipe 1 done done n y n n n y y y y y n (tp[3:2] = 11) (tp[3:2] = 10) (tp[3:2] = 10) (tp[3:2] = 00) (ep0 = 0) (ep0 = 1) n vr02127f
using the st7 universal serial bus microcontroller 26/38 figure 14. in token received by endpoint 0 a current transfer stage is data in stage? current transfer stage is last in transaction? device address to det after status stage? current transfer stage is: no data stage or last out transaction or data stage out? error data in stage status out stage set address w rite valid in the stat_rx[1:0] bits of the ep0rb register done n n n n y y y y vr02127g
27/38 using the st7 universal serial bus microcontroller figure 15. out token received by endpoint 0 n n y b current transfer stage is last in transaction? current transfer stage is data in stage? current transfer stage is data out stage? status out stage error w rite valid in the stat_rx[1:0] bits of the ep0rb register no more data to be received? stall endpoint0 data o ut stage next packet to receive will be the last of the transaction? w rite valid in the stat_rx[1:0] bits of the ep0rb register status in stage done done y y y y n n n vr02127h
using the st7 universal serial bus microcontroller 28/38 5.5.1 setup stage when a setup token is received, the firmware: 1. saves the next six bytes after the setup token 2. checks if the control transfer has a data stage or not 3. decodes the request sent by the host if the data transfer direction is from the device to the host, the firmware prepares data to be re- turned when the host sends an in token, otherwise it sets the hardware ready to receive data from the host. if there is no data transfer, the program jump to the status in routine.
29/38 using the st7 universal serial bus microcontroller figure 16. setup token received by endpoint 0 see chapter 9 usb device framework of the usb specification for detailed information on bmrequesttype and wlength. start save the 6 first bytes of the u sb device r equest wlength = 0 (no data stage) set usbctrstatus = no_data_stage received request is a standard request? received request is a class request? received request is a vendor request? d * * status in s tage done received request is a standard request? received request is a class request? received request is a vendor request? stall endpoint0 c * * bmrequesttype[7]= 1? write valid in the stat_rx[1:0] bits of the ep0rb register d at a in st ag e set u sbc trstatus = data_in_stage set u sbc trstatus = data_out_stage n n y y done n n n n n n y y y y y y *:not implemented vr02127i
using the st7 universal serial bus microcontroller 30/38 figure 17. standard request processing with data transfer see chapter 9 usb device framework of the usb specification for detailed information on brequest, wvalue and wlength. when the get_descriptor, get_configuration requests are received the function must return the appropriate descriptor. c brequest = get_descriptor or set_descriptor wvalue = device currentusbblenght = currentdescaddpointer = devdescsize wvalue = string currentusbblenght = currentdescaddpointer = devdescsize wvalue = configuration wvalue = device currentusbblength =confdescsize currentusbblengt h =wlength currentdescaddpointer = confdescsize wvalue=hid currentusbblength = hiddescsize currentdescaddpointer = hiddescadd wvalue=hid currentusbblength = reportdescsize currentdescaddpointer = reportdescadd brequest = get_interface brequest = get_status brequest = get_configuration stall enpoint0 done currentusbblength = wlength currentdescaddpointer = confvaladd currentusbblength = wlength currentdescaddpointer = interfacedescadd currentusbblength = wlength currentdescaddpointer = statusadd n n n n n n n n n y y y y y y y y y y vr02127j
31/38 using the st7 universal serial bus microcontroller if a descriptor has a length longer than eight bytes, multiple data stages are needed. two var- iables are used during the control transfer to return a descriptor stored in rom to the pc host: 1. currentusbblength specifies the current total number of bytes to transmit. 2. currentdescaddpointer specifies the current position of the descriptor pointer. for example, if a descriptor is 34 bytes long, four data in stages of 8 bytes and one of 2 bytes are needed to return the descriptor. currentusbblength is initialized to 34 and currentdescaddpointer indicates the starting posi- tion in the array containing the descriptor before the first in transfer. after every data in stage, currentusbblength and currentdescaddpointer are decreased in order to indicate the current byte number remaining and the current position of the pointer in the descriptor array respectively.
using the st7 universal serial bus microcontroller 32/38 figure 18. example of a 34 bytes long descriptor transfer time 34 26 18 10 2 in transfer #1 @#1 @#2 @#3 @#4 @#5 in transfer #2 in transfer #3 in transfer #4 in transfer #5 8 bytes 8 bytes 8 bytes 8 bytes 2 bytes time currentdescadpointer will point to address @#1 for the first in transfer, then to address @#2 for the second in transfer till address @#5 currentusbblength value
33/38 using the st7 universal serial bus microcontroller figure 19. standard request processing without data transfer d bre q uest = clear_feature bre q uest =set_feature bre q uest = set_address bre q uest = set_interface bre q uest = set_configuration stall endpoint0 clear feature done set configuration set interface set address set feature n n n n y y y y y n vr02127k
using the st7 universal serial bus microcontroller 34/38 5.5.2 data stages 5.5.2.1 data in stage figure 20. data in stage start currentusbblength<= maxpaketsize n currentusbblength== 0 n brequest = get_status n brequest = get_descriptor brequest = get_configuration n brequest = get_interface n error set usbctrstatus = last_in_trans g et interface get configuration get descriptor get status send 0 length data packet done y y y y y y n vr02127l
35/38 using the st7 universal serial bus microcontroller 5.5.2.2 data out stage figure 21. data out stage error bre q uest = set_descriptor set descriptor currentusbblen g th = 0 set usbctrstatus = last_out_trans i no_more_data start done n n y y vr02127m
using the st7 universal serial bus microcontroller 36/38 5.6 status stages 5.6.1 status in stage the function must return a zero length data packet in response to a in token for the status in stage. for a set_address request, the status in stage routine is somewhat different. the firmware must wait for the completion of the set_address request processing to assign to the device the unique address sent by the host since the transfers for this request are ad- dressed to the default address. a software flag is set if a set_address request is received. after completion of the control transfer, the firmware checks if this flag is set to write the unique address in the daddr register (see figure in token received by endpoint 0 ) figure 22. status in stage bre q uest = set_address usbctrstatus = address2set send 0 length data packet start done n y vr02127n
37/38 using the st7 universal serial bus microcontroller 5.6.2 status out stage when the last data in stage is performed, the firmware executes the status out stage rou- tine. this routine sets the st_out bit in the ep0ra register. when this bit is set, all non zero data transactions are stalled by hardware. when the out token of the status out stage is received, the status out stage routine is called and then clears the st_out bit. figure 23. status out stage 5.7 usb reset the usb reset routine is called when a usb reset signal has generated a usb reset interrupt. the firmware must then re-initialize the usb interface following this sequence: 1. set the starting address of the endpoint dma buffers 2. enable endpoint 0 in reception 3. write interrupt mask register 3. power on the internal 3.3v regulator to supply the external pull-up resistor used for detec- tion by a hub. 5.8 start of frame event this routine is called when a sof indication on the bus has generated a usb sof interrupt. see chapter 4.1.1 entering suspend state for detailed information. bre q uest = set_address usbctrstatus = address2set send 0 length data packet start done n y vr02127n
using the st7 universal serial bus microcontroller 38/38 the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connexion with their products. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com

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